Implementation of floating point fused basic arithmetic module using Verilog.
| Autor: | Patil, Ishan A., Balpande, Vishwas V., Meshram, Vijendra P., Chintwar, Ishan S. |
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| Zdroj: | 2015 International Conference on Communications & Signal Processing (ICCSP); 2015, p0100-0104, 5p |
| Databáze: | Complementary Index |
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