A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration.
| Autor: | Dickson, Timothy O., Liu, Yong, Agrawal, Ankur, Bulzacchelli, John F., Ainspan, Herschel, Toprak-Deniz, Zeynep, Parker, Benjamin D., Meghelli, Mounir, Friedman, Daniel J. |
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| Zdroj: | 2015 IEEE Custom Integrated Circuits Conference (CICC); 2015, p1-4, 4p |
| Databáze: | Complementary Index |
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