Schematic-Level and Layout-Level ESD EDA check methodology applied to smart power IC's - initialization and implementation.
| Autor: | Gevinti, Eleonora, Cerati, Lorenzo, Di Biccari, Leonardo, Ballarin, Giuseppe, Andreini, Antonio, Fragnoli, Mauro, Bogani, Antonio |
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| Zdroj: | 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD); 2015, p1-10, 10p |
| Databáze: | Complementary Index |
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