| Autor: |
Jin, Dong-Hwan, Kwon, Ji-Wook, Kim, Hyeon-June, Hwang, Sun-Il, Shin, Minchul, Cheon, Junho, Ryu, Seung-Tak |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Oct2015, Vol. 50 Issue 10, p2431-2440, 10p |
| Abstrakt: |
This paper presents a narrow-pitch readout circuit for multi-level phase change memory (PCM) employing an architecture of two-step 5 bit logarithmic ADC. A single-slope-architecture based fine ADC yields a 15 \mum-width compact single channel readout circuit for column parallel readout structure. A current-mode 2 bit flash ADC for coarse conversion and the pipelined architecture between the coarse and fine conversion enhance the readout rate up to 13 Mcells/sec. With the enhanced residue accuracy provided by the replica circuit of residue generator, the ADC achieves excellent linearity of 9.96 b (linear ADC equivalent). The integration-based residue generation effectively reduces circuit noise and yields 8.7 ENOB. The prototype chip was fabricated in a 65 nm CMOS process and the measured power consumption from a single channel readout circuit was 105 \muW at 13 Mcells/sec conversion rate at 1.2 V supply. [ABSTRACT FROM PUBLISHER] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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