Power optimization design for probabilistic logic circuits.
| Autor: | Xiao, Ran, Chen, Chunhong |
|---|---|
| Zdroj: | 2015 IEEE International Symposium on Circuits & Systems (ISCAS); 2015, p2593-2595, 3p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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| Autor: | Xiao, Ran, Chen, Chunhong |
|---|---|
| Zdroj: | 2015 IEEE International Symposium on Circuits & Systems (ISCAS); 2015, p2593-2595, 3p |
| Databáze: | Complementary Index |
| Externí odkaz: |
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