| Autor: |
Kustarev, Pavel, Antonov, Alexander, Pinkevich, Vasiliy, Yanalov, Roman |
| Předmět: |
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| Zdroj: |
Proceedings of the International Multidisciplinary Scientific GeoConference SGEM; 2015, Vol. 4, p407-414, 8p |
| Abstrakt: |
Using microprocessors and systems on a chip (SoC) for time-critical tasks, as well as processor, communication and memory IP cores, requires performance evaluation of their major data transfer channels. Since memory is considered as one of the main bottlenecks in current architectures, memory performance greatly influences the overall system performance. However, microarchitectural analysis of complex components can become difficult due to absence of open information about their internal organization. In the article, the method of selective evaluation of the cache memory components performance is proposed. The example of the applied real-time digital signal processing system, based on Multiprocess Cyclic Scheduling architectural model, developed by the authors, is considered. By this example the usage of the obtained information for system performance evaluation is demonstrated. This allows designing embedded systems with predictable performance characteristics and suits for time-critical embedded applications. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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