| Autor: |
Ramchan Woo, Chi-Weon Yoon, Jeonghoon Kook, Se-Joong Lee, Hoi-Jun Yoo |
| Předmět: |
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| Zdroj: |
IEEE Journal of Solid-State Circuits; Oct2002, Vol. 37 Issue 10, p1352, 4p, 4 Diagrams, 1 Chart, 2 Graphs |
| Abstrakt: |
Describes a 120-mW three-dimensional (3-D) rendering engine with 6-mB embedded DRAM and 3.2-GB/s runtime reconfigurable bus for personal digital assistant chip. Method of achieving the low power consumption; Fabrication of the 3-D rendering engine; Architecture and design; Logically local frame buffer and line-block memory mapping; Runtime configurable bus; Power reduction in frame buffer. |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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