| Autor: |
Roy, Apratim, Rashid, A.B.M.H. |
| Předmět: |
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| Zdroj: |
International Journal of Electronics; Sep2015, Vol. 102 Issue 9, p1535-1559, 25p |
| Abstrakt: |
A CMOS amplifier architecture is presented with a voltage lowering technique so that it can be driven from a single 0.7 V bias supply. The topology does not need scaled gate voltages (or additional bias circuits) and uses branching of its bias path to reduce power requirement. A three-stage cascaded structure is adopted for high gain with the output common-drain block realizing a gain control mechanism. The technique achieves 6 dB gain regulation (with a control voltage) at the expense of small additional power (1.27 mW). A K-band architecture is simulated with a 90-nm CMOS process to verify the proposed mechanisms. The low-power (7.37 mW) unregulated front-end achieves27 dB gain with a noise figure range of 2.99–3.06 dB within the 20.5–22.2 GHz bandwidth. Port reflection loss figures (and) are analysed to be−8 dB and−11 dB. The circuit has an area requirement of 0.62 mm2and performs better in terms of power supply requirement and potential packaging cost when compared with simulated results of published millimetre-wave amplifiers. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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