| Autor: |
Shacham, Ofer, Wachs, Megan, Danowitz, Andrew, Galal, Sameh, Brunhaver, John, Qadeer, Wajahat, Sankaranarayanan, Sabarish, Vassiliev, Artem, Richardson, Stephen, Horowitz, Mark |
| Zdroj: |
DAC Design Automation Conference 2012; 6/3/2012, p623-629, 7p |
| Abstrakt: |
Technology scaling has created a catch-22: technology now can do almost anything we want, but the NRE design costs are so high, that almost no one can afford to use it. Our current situation is reminiscent of the 1980's, when only a few companies could afford to produce custom silicon. Synthesis and placement and routing tools changed this, by providing modular tools with well defined interfaces that codified designer knowledge about the physical design of chips. Now we need a new set of tools that can codify designer knowledge about how to construct software, hardware, and validation to again enable application designers to produce chips. Researchers are developing methodologies that allow users to create hardware constructors, or generators. These include Genesis2, which extends SystemVerilog and enables the designer to encode hierarchical system construction procedurally. To demonstrate some of the capabilities that these languages and tools provide, we describe FPGen, a complete floating point generator written in Genesis2, that also generates the needed validation collateral and hints for the backend processes. [ABSTRACT FROM AUTHOR] |
| Databáze: |
Complementary Index |
| Externí odkaz: |
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