A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration.
| Autor: | Kim, Seonggeon, Kang, Jaehyun, Lee, Minjae |
|---|---|
| Zdroj: | 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC); 2014, p93-96, 4p |
| Databáze: | Complementary Index |
| Externí odkaz: |
|