이단으로 구성된 CMOS 전력증폭기 설계.

Autor: 배종석, 함정현, 정혜련, 임원섭, 조수호, 양영구
Zdroj: Journal of Korean Institute of Electromagnetic Engineering & Science / Han-Guk Jeonjapa Hakoe Nonmunji; Sep2014, Vol. 25 Issue 9, p895-902, 8p
Abstrakt: This paper presents a 2-stage CMOS power amplifier for the 1.75 GHz band using a 0.18-μm CMOS process. Using ADS simulation, a power gain of 28 dB and an efficiency of 45 % at an 1dB compression point of 27 dBm were achieved. The implemented CMOS power amplifier delivered an output power of up to 24.8 dBm with a power-added efficiency of 41.3 % and a power gain of 22.9 dB. For a 16-QAM uplink LTE signal, the PA exhibited a power gain of 22.6 dB and an average output power of 23.1 dBm with a PAE of 35.1 % while meeting an ACLR(Adjacent Channel Leakage Ratio) level of —30 dBc. [ABSTRACT FROM AUTHOR]
Databáze: Complementary Index