System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.
| Autor: | Chandrasekar, Karthik, Weis, Christian, Akesson, Benny, Wehn, Norbert, Goossens, Kees |
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| Zdroj: | Proceedings of the Conference: Design, Automation & Test in Europe; 3/18/2013, p236-241, 6p |
| Databáze: | Complementary Index |
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