Part VI: Memory Circuits: Section 7.2: Dedicated and Programmable Digital Signal Processors: A 1.8V 36mW DSP for the Half-Rate Speech CODEC.
| Autor: | Taketora Shiraishi, Koji Kawamoto, Kazuyuki Ishikawa, Hisakazu Sato, Fumiyasu Asai, Eiichi Teraoka, Toru Kengaku, Hidehiro Takata, Takeshi Tokuda, Kouichi Nishida, Kazunori Saitoh |
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| Zdroj: | Low-Power CMOS Design; 1998, p437-440, 4p |
| Databáze: | Complementary Index |
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