| Autor: |
Liang Y; School of Advanced Technology, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China.; Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3GJ, UK., Duan J; School of Advanced Technology, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China.; Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3GJ, UK., Zhang P; Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3GJ, UK.; Department of Communications and Networking, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China., Low KL; School of Advanced Technology, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China.; Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3GJ, UK., Zhang J; Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3GJ, UK.; School of Chips, Entrepreneur College (Taicang), Xi'an Jiaotong-Liverpool University, Suzhou 215123, China., Liu W; School of Advanced Technology, Xi'an Jiaotong-Liverpool University, Suzhou 215123, China.; Department of Electrical Engineering and Electronics, University of Liverpool, Liverpool L69 3GJ, UK. |
| Abstrakt: |
Devices under semi-on-state stress often suffer from more severe current collapse than when they are in the off-state, which causes an increase in dynamic on-resistance. Therefore, characterization of the trap states is necessary. In this study, temperature-dependent transient recovery current analysis determined a trap energy level of 0.08 eV under semi-on-state stress, implying that interface traps are responsible for current collapse. Multi-frequency capacitance-voltage (C-V) testing was performed on the MIS diode, calculating that interface trap density is in the range of 1.37×1013 to 6.07×1012cm-2eV-1 from EC-ET=0.29 eV to 0.45 eV. |
