| Autor: |
Bazzi HS; Electrical and Computer Engineering Department, Beirut Arab University, Debieh 1504, Lebanon., Jaber RA; Electrical and Electronic Engineering Department, Lebanese University, Hadath 40016, Lebanon., El-Hajj AM; Olayan School of Business, American University of Beirut, Beirut 1107, Lebanon., Hija FA; Cyber Security Graduate Program, Joaan Bin Jassim Academy for Defence Studies, Al Khor 50819, Qatar., Haidar AM; Electrical and Computer Engineering Department, Beirut Arab University, Debieh 1504, Lebanon. |
| Jazyk: |
angličtina |
| Zdroj: |
Micromachines [Micromachines (Basel)] 2024 Jul 31; Vol. 15 (8). Date of Electronic Publication: 2024 Jul 31. |
| DOI: |
10.3390/mi15080997 |
| Abstrakt: |
Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power-Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs. |
| Databáze: |
MEDLINE |
| Externí odkaz: |
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