| Autor: |
Alolaiyan O; Center of Excellence for Green Nanotechnologies, Microelectronics and Semiconductor Institute, King Abdulaziz City for Science and Technology, Riyadh 11442, Saudi Arabia., Albawardi S; Center of Excellence for Green Nanotechnologies, Microelectronics and Semiconductor Institute, King Abdulaziz City for Science and Technology, Riyadh 11442, Saudi Arabia., Alsaggaf S; Center of Excellence for Green Nanotechnologies, Microelectronics and Semiconductor Institute, King Abdulaziz City for Science and Technology, Riyadh 11442, Saudi Arabia., Tabbakh T; Center of Excellence for Green Nanotechnologies, Microelectronics and Semiconductor Institute, King Abdulaziz City for Science and Technology, Riyadh 11442, Saudi Arabia.; Department of Electrical and Computer Engineering, University of California Los Angeles, Los Angeles, California 90095, United States., DelRio FW; Material, Physical, and Chemical Sciences Center, Sandia National Laboratories, Albuquerque, New Mexico 87123, United States., Amer MR; Center of Excellence for Green Nanotechnologies, Microelectronics and Semiconductor Institute, King Abdulaziz City for Science and Technology, Riyadh 11442, Saudi Arabia.; Department of Electrical and Computer Engineering, University of Southern California, Los Angeles, California 90089, United States.; Department of Electrical and Computer Engineering, University of California Los Angeles, Los Angeles, California 90095, United States. |
| Abstrakt: |
Recent reports on machine learning and machine vision (MV) devices have demonstrated the potential of two-dimensional (2D) materials and devices. Yet, scalable 2D devices are being challenged by contact resistance and Fermi level pinning (FLP), power consumption, and low-cost CMOS compatible lithography processes. To enable CMOS + 2D, it is essential to find a proper lithography strategy that can fulfill these requirements. Here, we explored a modified van der Waals (vdW) deposition lithography and demonstrated a relatively new class of van der Waals field effect transistors (vdW-FETs) based on 2D materials. This lithography strategy enabled us to unlock high-performance devices evident by high current on-off ratio ( I on / I off ), high turn-on current density ( I on ), and weak FLP. We utilized this approach to demonstrate a gate-tunable near-ideal diode using a MoS 2 /WSe 2 heterojunction with an ideality factor of ∼1.65 and current rectification of 10 2 . We finally demonstrated a highly sensitive, scalable, and ultralow power phototransistor using a MoS 2 /WSe 2 vdW-FET for back-end-of-line integration. Our phototransistor exhibited the highest gate-tunable photoresponsivity achieved to date for white light detection with ultralow power dissipation, enabling ultrasensitive optoelectronic applications such as in-sensor MV. Our approach showed the great potential of modified vdW deposition lithography for back-end-of-line CMOS + 2D applications. |
