Projected performance of Si- and 2D-material-based SRAM circuits ranging from 16 nm to 1 nm technology nodes.

Autor: Lu YC; Graduate School of Advanced Technology, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan., Huang JK; Department of Systems Engineering, City University of Hong Kong, Kowloon, Hong Kong., Chao KY; Hong Kong Research Center, Huawei Technology Investment Co. Ltd, Kowloon, Hong Kong., Li LJ; Department of Mechanical Engineering and Department of Physics, The University of Hong Kong, Pokfulam, Hong Kong. lanceli1@hku.hk., Hu VP; Graduate School of Advanced Technology, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan. vitahu@ntu.edu.tw.
Jazyk: angličtina
Zdroj: Nature nanotechnology [Nat Nanotechnol] 2024 Jul; Vol. 19 (7), pp. 1066-1072. Date of Electronic Publication: 2024 Jun 21.
DOI: 10.1038/s41565-024-01693-3
Abstrakt: Researchers have been developing 2D materials (2DM) for electronics, which are widely considered a possible replacement for silicon in future technology. Two-dimensional transition metal dichalcogenides are the most promising among the different materials due to their electronic performance and relatively advanced development. Although field-effect transistors (FETs) based on 2D transition metal dichalcogenides have been found to outperform Si in ultrascaled devices, the comparison of 2DM-based and Si-based technologies at the circuit level is still missing. Here we compare 2DM- and Si FET-based static random-access memory (SRAM) circuits across various technology nodes from 16 nm to 1 nm and reveal that the 2DM-based SRAM exhibits superior performance in terms of stability, operating speed and energy efficiency when compared with Si SRAM. This study utilized technology computer-aided design to conduct device and circuit simulations, employing calibrated MoS 2 nFETs and WSe 2 pFETs. It incorporated layout design rules across various technology nodes to comprehensively analyse their SRAM functionality. The results show that, compared with three-dimensional structure Si transistors at 1 nm node, the planar 2DMFETs exhibited lower capacitance, leading to reduced cell read access time (-16%), reduced time to write (-72%) and lowered dynamic power (-60%). The study highlights the provisional benefits of using planar 2DM transistors to mitigate the performance degradation caused by reduced metal pitch and increased wire resistance in advanced nodes, potentially opening up exciting possibilities for high-performance and low-power circuit applications.
(© 2024. The Author(s), under exclusive licence to Springer Nature Limited.)
Databáze: MEDLINE
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