Ferroelectric FET-based context-switching FPGA enabling dynamic reconfiguration for adaptive deep learning machines.

Autor:	Xu Y; Pennsylvania State University, State College, PA 16802, USA., Zhao Z; University of Notre Dame, Notre Dame, IN 46556, USA., Xiao Y; Pennsylvania State University, State College, PA 16802, USA., Yu T; Pennsylvania State University, State College, PA 16802, USA., Mulaosmanovic H; GlobalFoundries Fab1 LLC & Co. KG, Dresden, Germany., Kleimaier D; GlobalFoundries Fab1 LLC & Co. KG, Dresden, Germany., Duenkel S; GlobalFoundries Fab1 LLC & Co. KG, Dresden, Germany., Beyer S; GlobalFoundries Fab1 LLC & Co. KG, Dresden, Germany., Gong X; National University of Singapore, Singapore 119077, Singapore., Joshi R; IBM Thomas J. Watson Research Center, Yorktown Heights, NY 10562, USA., Hu X; University of Notre Dame, Notre Dame, IN 46556, USA., Wen S; University of Southern California, Los Angeles, CA 90089, USA.; Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Beijing, China., Rios AS; University of Southern California, Los Angeles, CA 90089, USA., Lekkala K; University of Southern California, Los Angeles, CA 90089, USA., Itti L; University of Southern California, Los Angeles, CA 90089, USA., Homan E; Pennsylvania State University, State College, PA 16802, USA., George S; North Dakota State University, Fargo, ND 58102, USA., Narayanan V; Pennsylvania State University, State College, PA 16802, USA., Ni K; University of Notre Dame, Notre Dame, IN 46556, USA.
Jazyk:	angličtina
Zdroj:	Science advances [Sci Adv] 2024 Jan 19; Vol. 10 (3), pp. eadk1525. Date of Electronic Publication: 2024 Jan 17.
DOI:	10.1126/sciadv.adk1525
Abstrakt:	Field programmable gate array (FPGA) is widely used in the acceleration of deep learning applications because of its reconfigurability, flexibility, and fast time-to-market. However, conventional FPGA suffers from the trade-off between chip area and reconfiguration latency, making efficient FPGA accelerations that require switching between multiple configurations still elusive. Here, we propose a ferroelectric field-effect transistor (FeFET)-based context-switching FPGA supporting dynamic reconfiguration to break this trade-off, enabling loading of arbitrary configuration without interrupting the active configuration execution. Leveraging the intrinsic structure and nonvolatility of FeFETs, compact FPGA primitives are proposed and experimentally verified. The evaluation results show our design shows a 63.0%/74.7% reduction in a look-up table (LUT)/connection block (CB) area and 82.7%/53.6% reduction in CB/switch box power consumption with a minimal penalty in the critical path delay (9.6%). Besides, our design yields significant time savings by 78.7 and 20.3% on average for context-switching and dynamic reconfiguration applications, respectively.
Databáze:	MEDLINE
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