Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.

Autor:	Zhao Z; Rochester Institute of Technology, Rochester, New York 14623, United States., Deng S; Rochester Institute of Technology, Rochester, New York 14623, United States., Chatterjee S; University of Stuttgart, Stuttgart 70174, Germany.; Indian Institute of Technology Kanpur, Kanpur 208016, India., Jiang Z; Rochester Institute of Technology, Rochester, New York 14623, United States., Islam MS; Rochester Institute of Technology, Rochester, New York 14623, United States., Xiao Y; Pennsylvania State University, State College, Pennsylvania 16802, United States., Xu Y; Pennsylvania State University, State College, Pennsylvania 16802, United States., Meninger S; MIT Lincoln Laboratory, Lexington, Massachusetts 02421, United States., Mohamed M; MIT Lincoln Laboratory, Lexington, Massachusetts 02421, United States., Joshi R; IBM Thomas J. Watson Research Center, Yorktown Heights, New York 10598, United States., Chauhan YS; Indian Institute of Technology Kanpur, Kanpur 208016, India., Mulaosmanovic H; GlobalFoundries Fab1 LLC & Co. KG, Dresden 01109, Germany., Duenkel S; GlobalFoundries Fab1 LLC & Co. KG, Dresden 01109, Germany., Kleimaier D; GlobalFoundries Fab1 LLC & Co. KG, Dresden 01109, Germany., Beyer S; GlobalFoundries Fab1 LLC & Co. KG, Dresden 01109, Germany., Amrouch H; Technical University of Munich, Munich 80333, Germany.; Munich Institute of Robotics and Machine Intelligence, Munich 80992, Germany., Narayanan V; Pennsylvania State University, State College, Pennsylvania 16802, United States., Ni K; Rochester Institute of Technology, Rochester, New York 14623, United States.
Jazyk:	angličtina
Zdroj:	ACS applied materials & interfaces [ACS Appl Mater Interfaces] 2023 Nov 29; Vol. 15 (47), pp. 54602-54610. Date of Electronic Publication: 2023 Nov 14.
DOI:	10.1021/acsami.3c07827
Abstrakt:	Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage ( V TH ) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high- V TH state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low- V TH state stability. Comprehensive theoretical and experimental validation has been performed on fully depleted silicon-on-insulator (FDSOI) FeFETs integrated on a 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the nonferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.
Databáze:	MEDLINE
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