| Autor: |
Wang X; Wenzhou Institute of Hangzhou Dianzi University, Wenzhou 325024, China.; School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China., Zhang X; School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China., Dong C; School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China., Nath SK; School of Photovoltaic and Renewable Energy Engineering, University of New South Wales (UNSW Sydney), Kensington, NSW 2052, Australia., Iu HH; School of Engineering, The University of Western Australia, Crawley, WA 6009, Australia. |
| Abstrakt: |
This paper proposes a unique memristor-based design scheme for a balanced ternary digital logic circuit. First, a design method of a single-variable logic function circuit is proposed. Then, by combining with a balanced ternary multiplexer, some common application-type combinational logic circuits are proposed, including a balanced ternary half adder, multiplier and numerical comparator. The above circuits are all simulated and verified in LTSpice, which demonstrate the feasibility of the proposed scheme. |
