Network-on-Chip Irregular Topology Optimization for Real-Time and Non-Real-Time Applications.

Autor:	Oliveira SDS; Department of Computer Science and Applied Mathematics, Federal University of Rio Grande do Norte, Natal 59078-970, Brazil., Carvalho BM; Department of Computer Science and Applied Mathematics, Federal University of Rio Grande do Norte, Natal 59078-970, Brazil., Kreutz ME; Department of Computer Science and Applied Mathematics, Federal University of Rio Grande do Norte, Natal 59078-970, Brazil.
Jazyk:	angličtina
Zdroj:	Micromachines [Micromachines (Basel)] 2021 Sep 30; Vol. 12 (10). Date of Electronic Publication: 2021 Sep 30.
DOI:	10.3390/mi12101196
Abstrakt:	Network-on-Chip is a good approach to working on intra-chip communication. Networks with irregular topologies may be better suited for specific applications because of their architectural nature. A good design space exploration can help the design of the network to obtain more optimized topologies. This paper proposes a way of optimizing networks with irregular topologies through the use of a genetic algorithm. The network proposed here has heterogeneous routers that aim to optimize the network and support applications with real-time tasks. The goal is to find networks that are optimized for average latency and percentage of real-time packets delivered within the deadline. The results show that we have been able to find networks that can deliver all the real-time packets, obtain acceptable latency values, and shrink the chip area.
Databáze:	MEDLINE
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