Stateful Three-Input Logic with Memristive Switches.

Autor: Siemon A; Institut für Werkstoffe der Elektrotechnik II (IWE II), RWTH Aachen University, Sommerfeldstr. 24, 52074, Aachen, Germany.; JARA-Fundamentals for Future Information Technology, Jülich, Germany., Drabinski R; Institut für Werkstoffe der Elektrotechnik II (IWE II), RWTH Aachen University, Sommerfeldstr. 24, 52074, Aachen, Germany.; JARA-Fundamentals for Future Information Technology, Jülich, Germany., Schultis MJ; Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, 75080, Texas, USA., Hu X; Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, 75080, Texas, USA., Linn E; Institut für Werkstoffe der Elektrotechnik II (IWE II), RWTH Aachen University, Sommerfeldstr. 24, 52074, Aachen, Germany.; JARA-Fundamentals for Future Information Technology, Jülich, Germany., Heittmann A; Peter Grünberg Institut 10 (PGI-10) Forschungszentrum Jülich GmbH, Jülich, Germany., Waser R; Institut für Werkstoffe der Elektrotechnik II (IWE II), RWTH Aachen University, Sommerfeldstr. 24, 52074, Aachen, Germany.; JARA-Fundamentals for Future Information Technology, Jülich, Germany.; Peter Grünberg Institut 10 (PGI-10) Forschungszentrum Jülich GmbH, Jülich, Germany.; Peter Grünberg Institut 7 (PGI-7) Forschungszentrum Jülich GmbH, Jülich, Germany., Querlioz D; Centre de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Sud, Université Paris-Saclay, Palaiseau, 91120, France., Menzel S; JARA-Fundamentals for Future Information Technology, Jülich, Germany. st.menzel@fz-juelich.de.; Peter Grünberg Institut 7 (PGI-7) Forschungszentrum Jülich GmbH, Jülich, Germany. st.menzel@fz-juelich.de., Friedman JS; Department of Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, 75080, Texas, USA.; Centre de Nanosciences et de Nanotechnologies, CNRS, Univ. Paris-Sud, Université Paris-Saclay, Palaiseau, 91120, France.
Jazyk: angličtina
Zdroj: Scientific reports [Sci Rep] 2019 Oct 10; Vol. 9 (1), pp. 14618. Date of Electronic Publication: 2019 Oct 10.
DOI: 10.1038/s41598-019-51039-6
Abstrakt: Memristive switches are able to act as both storage and computing elements, which make them an excellent candidate for beyond-CMOS computing. In this paper, multi-input memristive switch logic is proposed, which enables the function X OR (Y NOR Z) to be performed in a single-step with three memristive switches. This ORNOR logic gate increases the capabilities of memristive switches, improving the overall system efficiency of a memristive switch-based computing architecture. Additionally, a computing system architecture and clocking scheme are proposed to further utilize memristive switching for computation. The system architecture is based on a design where multiple computational function blocks are interconnected and controlled by a master clock that synchronizes system data processing and transfer. The clocking steps to perform a full adder with the ORNOR gate are presented along with simulation results using a physics-based model. The full adder function block is integrated into the system architecture to realize a 64-bit full adder, which is also demonstrated through simulation.
Databáze: MEDLINE
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