| Autor: |
Ramanayaka AN; National Institute of Standards & Technology, Gaithersburg, Maryland, 20899, USA. aruna.ramanayaka@nist.gov., Kim HS; National Institute of Standards & Technology, Gaithersburg, Maryland, 20899, USA.; Department of Electrical and Computer Engineering, University of Maryland, College Park, Maryland, 20742, USA., Tang K; National Institute of Standards & Technology, Gaithersburg, Maryland, 20899, USA.; Department of Materials Science and Engineering, University of Maryland, College Park, Maryland, 20742, USA., Wang X; National Institute of Standards & Technology, Gaithersburg, Maryland, 20899, USA.; Chemical Physics Program, University of Maryland, College Park, Maryland, 20742, USA., Silver RM; National Institute of Standards & Technology, Gaithersburg, Maryland, 20899, USA., Stewart MD Jr; National Institute of Standards & Technology, Gaithersburg, Maryland, 20899, USA., Pomeroy JM; National Institute of Standards & Technology, Gaithersburg, Maryland, 20899, USA. joshua.pomeroy@nist.gov. |
| Abstrakt: |
Using photolithographically defined implant wires for electrical connections, we demonstrate measurement of a scanning tunneling microscope (STM) patterned nanoscale electronic device on Si(100). By eliminating onerous alignment and complex lithography techniques, this approach is accessible to researchers in smaller efforts who may not have access to tools like electron beam lithography. Electrical contact to the nanodevices is achieved by implanting patterned, degenerately doped wires in the substrate using photolithography and commercial low energy ion implantation. We bring several isolated, implanted wires to within the STM scanner's field of view where the STM can detect and smoothly draw contiguous patterns that directly overlap with implant lines for electrical connections. This overlapping provides a two-dimensional (2D) overlap interface with the 2D electron system, in contrast to many state-of-the-art methods that rely on contacting an exposed edge. After the STM pattern is phosphine dosed and overgrown with silicon, photolithography is then used again to align (≈ 160 μm) 2 aluminum contact pads onto (≈ 200 μm) 2 implanted areas at the ends of the wires. We present detailed results that optimize the spacing of neighboring wires while maintaining electrical isolation after heating to > 1200 °C, a step required for in situ Si surface preparation. |
