| Autor: |
Trivedi T; Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin , Austin, Texas 78758, United States., Roy A; Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin , Austin, Texas 78758, United States., Movva HCP; Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin , Austin, Texas 78758, United States., Walker ES; Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin , Austin, Texas 78758, United States., Bank SR; Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin , Austin, Texas 78758, United States., Neikirk DP; Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin , Austin, Texas 78758, United States., Banerjee SK; Microelectronics Research Center, Department of Electrical and Computer Engineering, The University of Texas at Austin , Austin, Texas 78758, United States. |
| Abstrakt: |
As the focus of applied research in topological insulators (TI) evolves, the need to synthesize large-area TI films for practical device applications takes center stage. However, constructing scalable and adaptable processes for high-quality TI compounds remains a challenge. To this end, a versatile van der Waals epitaxy (vdWE) process for custom-feature bismuth telluro-sulfide TI growth and fabrication is presented, achieved through selective-area fluorination and modification of surface free-energy on mica. The TI features grow epitaxially in large single-crystal trigonal domains, exhibiting armchair or zigzag crystalline edges highly oriented with the underlying mica lattice and only two preferred domain orientations mirrored at 180°. As-grown feature thickness dependence on lateral dimensions and denuded zones at boundaries are observed, as explained by a semiempirical two-species surface migration model with robust estimates of growth parameters and elucidating the role of selective-area surface modification. Topological surface states contribute up to 60% of device conductance at room temperature, indicating excellent electronic quality. High-yield microfabrication and the adaptable vdWE growth mechanism with readily alterable precursor and substrate combinations lend the process versatility to realize crystalline TI synthesis in arbitrary shapes and arrays suitable for facile integration with processes ranging from rapid prototyping to scalable manufacturing. |
