Settling optimised sample-and-hold circuit with high-linearity input switch in 65 nm CMOS.
| Autor: | Shu, G., Shu, C., Fan, M., Ren, J. jyren@fudan.edu.cn |
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| Zdroj: | Electronics Letters (Institution of Engineering & Technology). 10/28/2010, Vol. 46 Issue 22, p1485-1486. 2p. 3 Diagrams, 3 Graphs. |
| Databáze: | Business Source Ultimate |
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