Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems.
| Autor: | Yanagawa, Yoshimitsu1 yanagawa@isas.jaxa.jp, Kobayashi, Daisuke2 d.kobayashi@isas.jaxa.jp, Ikeda, Hirokazu2 ikeda.hirokazu@jaxa.jp, Saito, Hirobumi3 hirose@isas.jaxa.jp, Hirose, Kazuyuki2 koubun@isas.jaxa.jp |
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| Zdroj: | IEEE Transactions on Nuclear Science. Aug2008 Part 1 of 2, Vol. 55 Issue 4, p1947-1952. 6p. 9 Diagrams, 1 Chart. |
| Databáze: | Business Source Ultimate |
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