Circuit Simulation of Threshold-Voltage Degradation in a-Si:H TFTs Fabricated at 175 °C.
| Autor: | Shringarpure, Rahul1 rahul.shringarpure@asu.edu, Venugopal, Sameer2 Sameer.Venugopal@asu.edu, Zi Li2 Zi.Li@asu.edu, Clark, Lawrence T.1 Lawrence.Clark@asu.edu, Allee, David R.1 David.Allee@asu.edu, Bawolek, Edward2 Edward.Bawolek@asu.edu, Toy, Daniel2 Dan.Toy@asu.edu |
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| Zdroj: | IEEE Transactions on Electron Devices. Jul2007, Vol. 54 Issue 7, p1781-1783. 3p. 1 Diagram, 1 Chart, 1 Graph. |
| Databáze: | Business Source Ultimate |
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