Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.
| Autor: | Lingappan, Loganathan1 llingapp@princeton.edu, Ravi, Srivaths2 sravi@nec-Iabs.com, Raghunathan, Anand2 anand@nec-labs.com, Jha, Niraj K.2 jha@princeton.edu, Chakradhar, Srimat T.1 chak@neciabs.com |
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| Zdroj: | IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems. Oct2006, Vol. 25 Issue 10, p2193-2206. 14p. 2 Diagrams, 6 Charts, 4 Graphs. |
| Databáze: | Business Source Ultimate |
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