FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder.
| Autor: | Thamizharasan, V.1 (AUTHOR) ecetamil@gmail.com, Kasthuri, N.2 (AUTHOR) |
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| Zdroj: | International Journal of Electronics. Aug2024, Vol. 111 Issue 8, p1253-1265. 13p. |
| Databáze: | Business Source Ultimate |
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