FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier.
| Autor: | Thamizharasan, V.1 (AUTHOR) ecetamil@gmail.com, Kasthuri, N.2 (AUTHOR) |
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| Zdroj: | International Journal of Electronics. Apr2023, Vol. 110 Issue 4, p587-607. 21p. |
| Databáze: | Business Source Ultimate |
| Externí odkaz: |
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