Modeling of Via Resistance for Advanced Technology Nodes.

Autor:	Ciofi, Ivan1, Roussel, Philippe J.1, Saad, Yves2, Moroz, Victor2, Hu, Chia-Ying1, Baert, Rogier1, Croes, Kristof1, Contino, Antonino1, Vandersmissen, Kevin1, Gao, Weimin2, Matagne, Philippe1, Badaroglu, Mustafa3, Wilson, Christopher J.1, Mocuta, Dan1, Tokei, Zsolt1
Zdroj:	IEEE Transactions on Electron Devices. May2017, Vol. 64 Issue 5, p2306-2313. 8p.
Databáze:	Business Source Ultimate
Externí odkaz:	Zobrazit plný text záznamu