Design and Investigation of Junction-less TFET (JL-TFET) for the Realization of Logic Gates.
| Autor: | Shah, Bhushit1 (AUTHOR) bhushitshah899@gmail.com, Singh, Prabhat1 (AUTHOR) prabhat@nith.ac.in, Raman, Ashish1 (AUTHOR) ramana@nitj.ac.in, Singh, Nagendra Pratap2 (AUTHOR) singhnp@nitj.ac.in |
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| Zdroj: | NANO. Nov2024, p1. 12p. |
| Databáze: | Academic Search Ultimate |
| Externí odkaz: |
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