2b/cycle-Assisted 10-bit SAR ADCs
| Autor: | Hua-Wei Tseng, 曾華偉 |
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| Rok vydání: | 2018 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 106 This thesis presents 2b/cycle-assisted 10-bit successive approximation register (SAR) analog-to-digital converters (ADCs). By applying 2b/cycle-assisted architecture, it reduces the number of conversion cycles and thus speeds up the ADC operation. The proposed dynamic register (MdREG) circuit cuts down the delay from the comparator output to the DAC switches. It also helps the ADC operate at higher sampling rates. Dual-reference C-DACs are proposed to avoid using a tiny unit capacitance. It also reduces the total capacitance of the digital-to-analog converter (DAC). The offset calibration scheme is proposed to effectively alleviate the degradation of the ADC linearity. Two ADCs were implemented based on the proposed 2b-1b/cycle configuration. A 10-bit 100-MS/s SAR ADC was fabricated using a 180 nm CMOS technology. This ADC occupies an active area of 0.07 mm2. Operating at 100-MS/s, the ADC consumes 7.4 mW from a 1.9 V supply. The peak DNL and INL are -0.56/+0.67 LSB and -0.75/+0.79 LSB respectively. The measured Nyquist SNDR and SFDR are 52.2 dB and 75.2 dB respectively. Another 10-bit 500-MS/s ADC was implemented in 40nm CMOS. Operating at 500-MS/s, the ADC consumes 1.84 mW from a 0.9 V supply. The simulated Nyquist SNDR and SFDR are 59.6 dB and 76 dB respectively. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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