Design of Frequency-Locked Loop and Track-and-Hold Amplifier
| Autor: | Shu-Yan Huang, 黃書彥 |
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| Rok vydání: | 2015 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 103 This thesis focuses on the sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with frequency-locked loop (FLL) for microwave and millimeter-wave applications and the high speed track-and-hold amplifier (THA) for front-end of analog-to-digital converter (ADC). The analysis, simulation and measurement of the SILVCO with FLL are presented in Chapter 2 and 3, respectively. The design and analysis of a broadband CMOS THA are proposed in Chapter 4. The theoretical model of SILVCO with FLL are proposed in Chapter 2. The transfer functions of the other blocks in SILVCO with FLL are presented. The SILVCO with FLL is designed using the proposed model, and the calculated results are presented to verify the loop stability. The proposed SILVCO with FLL demonstrates good robustness versus process, voltage, and temperature variations. The proposed SILVCO with FLL is fabricated using TSMC 90 nm CMOS general purpose (GP) process. The measurements of the SILVCO with FLL and phase-locked loop (PLL) are completely presented. As the output frequency is 10.4 GHz, the proposed SILVCO with FLL features a phase noise of -130.38 dBc/Hz and the minimum jitter features 30.25 fs when output frequency is 10.3 GHz. The dc power consumption of the proposed SILVCO with FLL is 26 mW. The design and analysis of the proposed THA are presented in Chapter 4. The distributed amplifier (DA) is adopted to enhance the bandwidth of the proposed THA. The dummy switch topology is also adopted in the track-and-hold stage to avoid the charge injection. The cascode amplifier is used to enhance the linearity of the proposed THA. The proposed THA is fabricated using TSMC 90 nm CMOS low power (LP) CMOS process. The proposed THA features a 3-dB bandwidth from 0 to 17 GHz. The measured spurious-free dynamic ranges (SFDR) of the proposed THA are -42.1 dB and -41.9 when the sampling rates are 12 GS/s and 6 GS/s, respectively. The dc power consumption of the proposed THA is 216 mW. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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