Metastability characterization and multi-stage synchronizer design
| Autor: | Hsu, Wei-Min, 徐維旻 |
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| Rok vydání: | 2014 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 102 As the semiconductor technology continue to evolve, large number of transistors can be placed onto a single chip, and thus more complex functions can be implemented. A trend in implementing these complex systems on a chip is to divide the system into subsystems that each subsystem can have different power supply values and different clock frequencies to save power while maintaining the performance. Therefore, data transfer between different clock domains is becoming a norm in today’s large digital IC’s. When the asynchronous data (from different clock domain) arrives within the register’s setup-hold window, the data cannot be reliability received. And thus, it would cause a reliability issue. Synchronizers are usually added in between different domains to minimize data transfer errors. We investigate the synchronizer circuits, which usually consist of multi-stage registers, and characterize the mean-time-between-failure (MTBF) as a function of register’s parameters. We find that the MTBF is dominated by the resolution time constant of the last stage register, no matter how many stages in the synchronizer. Extensive simulations that include corner conditions, post-layout simulation and different technology generations, all confirm this finding. With this finding, we can optimize the synchronizer design to increase MTBF while reducing power consumptions or area. Using TSMC 65LP technology, we have observed 20% power reduction while maintaining similar MTBF or 12% area reduction in a three stage mixed type synchronizer. This principle can be applied to any future synchronizer design. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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