A Study of High Voltage Gate to Gate Coupling Floating Field Plate MOSFET by CMOS nano-scale Process
| Autor: | 李子寬 |
|---|---|
| Rok vydání: | 2014 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 102 Over the past few decades, the importance of sustainable development had been rooted in people’s mind deeply. Therefore, the energy harvesting and power IC technology becomes the key issues. How to get a good balance between the breakdown voltage and the on-resistance is critical in designing power devices. Typical power devices are fabricated by special process that need the extra wire bonding to connect the system circuit and the power device. So the high cost is a major problem of this. The general MOSFET’s breakdown voltage is affected by surface peak electric field. It causes the MOSFET’s gate dielectric reliability getting worse. In the previous work, a Floating Field Plate MOSFET (FFP-MOSFET) was fabricated by 28nm CMOS process. With floating gate as its field plate, its depletion region will be extended, reduces the drain-side peak electric-field. However, FFPMOS suffers from large on-resistance. This work presents a GGCFFPMOS which introduce external capacitors between the floating gates. Measurement results show that gated-breakdown voltage is successfully extended. Furthermore, the trade-off between the breakdown voltage and the on-resistance improves. Without special process defined drift region or extra masks, this device is formed by pure logic process and allow for high flexibility. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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