An Embedded System Design for Arc-Based Fractal Coding
| Autor: | Chen-Kai Kao, 高振凱 |
|---|---|
| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 Image compression technology has long been an important part in image processing, since uncompressed image files usually take up huge amount of storage space and are very time-consuming to transfer through networks. The arc-based fractal coding is a near lossless image compression technique suitable for medical and geographic imaging applications. This thesis presents the design and implementation of an embedded system for arc-based fractal coding. For the embedded system to benefit from hardware acceleration while preserving the flexibility of software implementation, we adopt a hardware/software integrated design approach. The arc-based fractal coding works as follows. In the encoding phase, an image is partitioned into a collection of range blocks, and a set of arcs are created. The best match for a given range block is searched in the set of arcs. The set of affine transformations is then stored in a codebook. In the decoding phase, the image is reconstructed iteratively according to the codebook. In this research, both the grayscale image transformation and the generation of fractal code are implemented in hardware circuits. The rest of the processing is done in software, which has been developed on the Nios II IDE. To strengthen the system capability, we have also ported a version of μClinux OS. For performance reason, we select the fast-type Nios II CPU which operates at a clock rate of 50 MHz. With the Altera SOPC technology, hardware modules are integrated into the Nios II processing environment through the Avalon Bus architecture. Our hardware implementation platform is Terasic DE2-35 development board featuring an Altera Cyclone II FPGA EP2C35F672C6. A total of 100 medical or fractal image samples have used for function verification. Experimental results show that all images can be compressed and reconstructed almost perfectly. The average processing time per image is about 1.5 seconds. With hardware and software working together, processing speed gain is 6.6-fold over pure software implementation, given that the program is executed on the Nios II platform. The experiment shows that the proposed embedded system design and implementation has succeeded in executing the arc-based fractal coding scheme. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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