A BIST Strategy for 3D Network-on-Chip Application
| Autor: | Min-Ju Chan, 詹旻儒 |
|---|---|
| Rok vydání: | 2011 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 99 When the consumer electronic products will be more lightweight and portable, the conception of system-on-chip (SoC) technology is widely used. Therefore, the network-on-chip (NoC) becomes the key technology for enhancing the overall performance of SoC, and that is a good opportunity for getting development. In the pursuit of high performance goals, how to insert more component modules into a chip has become a subject of study. That also shows the importance of three-dimensional (3D) stacked technology. However, the development of miniaturization of process technology and advancement of stacked technology can make more complex for configuration and routing. It can let the fault incidence of overall SoC design to increase, and it will be the resistance for achieving the 3D NoC. Therefore, this paper proposes a built-in self-test (BIST) strategy for 3D NoC application. By using a regular partition method, it can simplify the test complexity of 3D NoC. Moreover, it also provides a complete BIST flow to detect the interconnection fault in the 3D NoC. For verifying the validity of the testing strategy that the paper proposes, we use the simulation and data analysis. And then, we achieve good coverage in fault detection. The result proves that the test strategy has a good performance for detecting fault. Moreover, this BIST strategy can also be applied the 3D NoC architecture in different sizes. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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