The Latent Defect Activation Analysis of DVS in nanotech Cu Process
| Autor: | Wen-Chi Chou, 周文祺 |
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| Rok vydání: | 2009 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 97 Semiconductor technology which has hundreds of process steps during integrated chip manufacturing is a complicated field and it covers physics, chemistry, thermionics, dynamics and mechanics fundamentals. Defects would be generated during manufacturing and should be able to caught by traditional wafer sorting program, however, some latent defects would not be observed at early stage easily until chip is malfunction or degradation. Many approaches to detect and screen the latent defects have been discussing. In the era of Cu process, optimization of the acceleration factor is the key to present the failure mode under accelerated life time test. Facing the continuously device dimension shrinkage, the defects are no more a static state, but will be easily to induce the timing delay which cannot be gated one hundred percent with traditional sorting procedure. To employ the voltage and temperature acceleration factor into the dynamic test sequence and datalog analysis will be helpful to activate latent defects and detect their existence in the following tests. In the thesis, the reliability engineering principles, acceleration life time test and digital integrated chip testing methodologies will be initially introduced. The evolution of semiconductor industry and the benefit with Cu techniques of the deep submicron process will be illustrated as well. Then, to understand the major mechanisms of defects generation will be good to extract the optimized DVS condition for latent defect activation and detection. Conclusion will be summarized at last. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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