Algorithms and VLSI Architecture Design of Wavelet Related Signal Processing
| Autor: | Chung-Hsien Yang, 楊宗憲 |
|---|---|
| Rok vydání: | 2007 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 96 This dissertation presents a research on wavelet transform and signal subspace speech enhancement from algorithms to hardware implementations. In the design of algorithms, we present three subspace-based approaches for speech enhancement. These approaches are signal subspace speech enhancement using wavelet packet expansion (SSUW), speech enhancement using critical band and subspace tracking (CBST), and SNR and auditory masking aware technique for multiband speech enhancement (SAMA). The decomposition of signal subspace is a time-consuming processing. In the algorithm of SSUW, we utilize wavelet packet to perform approximate Karhunen-Loeve transform, i.e., fast eigendecomposition for signal subspace speech enhancement to overcome this problem. In the algorithm of CBST, we incorporate a perceptual wavelet filterbank that is derived from psycho-acoustic model with signal subspace processing. The projection approximation subspace tracking deflation (PASTd) algorithm is used to track the signal subspace. The experimental results which were obtained by testing TAICAR databases show that this approach is better than conventional subspace methods. The low frequency noises in car noisy environments are suppressed efficiently after applying the perceptual filterbank and subspace processing. In the algorithm of SAMA, we focus our design on the gain adaptation of each critical band. The gain adaptation plays a crucial role in the critical band signal estimation. An attenuation factor based on auditory masking and prior SNR of each critical band is presented to adjust the estimator’s gain. According to the experimental evaluation, our method achieved enhancement performances better than conventional subspace and spectral subtraction methods. In the design of VLSI architecture, a hardware design of 2D discrete wavelet transform (DWT) and system-on-a-programmable-chip (SoPC) architecture of subspace based speech enhancement are presented respectively. 2D DWT architectures can be classified into line-based and block-based architectures. Line-based architectures are simple with low complexity. They are efficient for 1D applications. In case of 2D transforms, they suffer from two main problems: memory requirements and latency. These problems are inherent in line-based architectures. In this dissertation, a novel block-based architecture for computing the lifting-based 2-D DWT coefficients is presented. This architecture makes the significant reduction of buffer size and speeds up the calculation of 2D wavelet coefficients as compared with those line-based fashion architectures. In addition, the proposed architecture supports the JPEG2000 default filters and the hardware utilization is nearly 100%. As compared with line-based architectures, the latency is reduced from N^2 down to 3N. The architecture has been realized in ARM-based ALTERA EPXA10 Development Board with frequency at 44.33MHz. For real-time speech enhancement, a SoPC architecture and VLSI design of the PASTd algorithm are proposed. To realize pipeline computation, we present a pipelined PASTd algorithm without data-dependent hazards. The maximum clock rate is 9.7 MHz and the typical clock rate which achieves real time requirement is 4.6 MHz. The corresponding architecture was also experimentally verified via an ALTERA EPXA10 development board. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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