The Design and Implememtation of two port RAM and 1T-SRAM
| Autor: | Chien-Te Wang, 王建德 |
|---|---|
| Rok vydání: | 2007 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 95 To reduce the chip cost is the most important issue for an IC design house to survive in the very competitive IC industry. Scaling down the chip area is an very effective way to reduce the chip cost. The random access memorys (RAM) usually occupy large chip area in the system on chip (SOC) design, therefore we use 1T-SRAM to replace the traditional 6T-SRAM in this thesis. 1T-SRAM has several advantages. It could be made by standard logic manufacturing process. It’s interface is compatible with standard SRAM. The most important issue is that it’s area is much smaller than that of 6T-SRAM. The two-port RAM which is applied in designing 8051 single chip of pipeline structure is also designed in this thesis. Most instructions of this single chip can be executed in one clock cycle. It’s performance has greatly improved as compare to traditional 8051 which need 12 clock cycles to execute one instruction. It has following characteristics : Using single clock cycle, one port write, and the other port read. Another significant difference is to use single clock cycle, which is capable of reading and writing the same address at same time. Usually the two-port RAM made by memory complier has two kinds of clock cycles. there must be existing a time difference between these two kinds of clock cycles, while we read and write the same address at the same time. This disadvantage often greatly bothers the system integrating designers. Key Words ： sense amplifier、SA 、 SRAM. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
| Externí odkaz: |
|