All Digigtal Time-To-Digital Converter
| Autor: | Jui-Yi Tsai, 蔡宜叡 |
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| Rok vydání: | 2007 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 95 The proposed high resolution Time to Digital Converter (TDC) has a resolution between 1.6ps~16ps, and has an input range between 0.4ns ~ 2.01ns which is equivalent to a frequency of 2.5GHz and 500MHz respectively. The architecture can operate with a frequency 500MHz~2.5GHz. The circuit is implemented using TSMC 0.18um 1P6M CMOS process. The architecture adopts two stages to increase the conversion rate about 5ns with a reference frequency of 255MHz~290MHz. The architecture is based on all digital using a DLL which has the advantage of conventional designs and also an adjustable resolution, obtaining low area overhead and low power dissipation. As the DLL is locked, the output signal changes according to different input pulse width, and obtaining 9 bits output code instantly which is real time. The proposed architecture can be used as Frequency to Digital Converter (FDC), the effect of the jitter of a periodic signal is reduced as increasing the stages of the DLL achieving the resolution of the FDC. The proposed architecture is implemented using TSMC 0.18um 1P6M CMOS process. The core area is 0.547×0.271mm2 and the total power dissipation is 6.84mW. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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