A Platform for High-Level Synthesis and Post-Simulation of Self-Timed Systems
| Autor: | Sung-Min Lin, 林嵩閔 |
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| Rok vydání: | 2006 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 94 We propose an asynchronous platform which allows FPGA board docking onto an Arm-based development kit to simulate and verify the VHDL-compatible coding styles in the synthesis. This high-level synthesis targets on the self-timed circuit implementation technique since asynchronous design is gradually adapted to the circuit engineering alternatives. The self-timed system design methodology lacks of complete tool set to cover the entire engineering design processes; therefore, varieties of applicable software are created and left un-integrated. We set up a design flow to stricken the asynchronous design methodology by reducing the complexity of transforming channel-level to handshaking-level in the high-level synthesis and simulation. The feasibility of a successful asynchronous design methodology depends on completeness of series of software simulations and hardware verification. Thus, we impose a rigid guideline for VHDL programming on conversion of channel package to 4-phase handshaking protocol and later separate the programmed design into controller and datapath by syntax property. Further to the translation of the program, we use 3D plus timing information modeling and tools for datapath optimization in the final synthesis. In the end, the design verification will be downloaded to FPGA for circuit simulation, and the test patterns or the testbench will be loaded to the development kit or the platform we have established in order to compare the actual result with our desired signal patterns on the platform. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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