FPGA Implementation and Design of a Low-Cost and HighPerformance AES Processor
| Autor: | Yu-Hsin Lu, 陸育新 |
|---|---|
| Rok vydání: | 2006 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 94 The Advanced Encryption Standard was accepted as a FIPS standard in November 2001. Since then, there have been many different hardware implementations for ASIC and FPGA. But how to find out the suitable design according to the demand has become an important topic. In this thesis, composite field arithmetic of the SubBytes/InvSubBytes transformation is employed to reduce the area requirements and the hardware complexity. We try to reduce the composite field architecture of the SubByte transformation which proposed by K.K. Parhi. Meanwhile, in the key scheduling unit, we modify parts of the offline key scheduling architecture. This way the area and hardware complexity are reduced significantly. Moreover, we implement the architecture of a fully pipelined AES encryption processor on a single chip FPGA. By using inner-round and outer-round pipelining techniques with 7 substages in each round unit can achieve a through- put of 31.34 Gbps on a Xilinx XC2VP20-7 device in non-feedback modes. The area cost is reduced by 15% in terms of equivalent throughput/slice than the architecture, which proposed by K.K. Parhi. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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