A 14-bit 200MS/s Digital to Analog Converter Design
| Autor: | Tzung-Shen Chen, 陳宗申 |
|---|---|
| Rok vydání: | 2004 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 92 Demand for high-speed and high-resolution digital—analog converters (DACs) continues to grow every year, driven primarily by strong growth in the markets for wired communication systems such as broadband modems employing emerging standards like xDSL, and wireless communications systems such as mobile cellular networks. Such applications require DACs to be capable of handling data at speeds of several tens or hundreds of MS/s, with data word resolution on the order of 10—14 bits. In this thesis, a 14-bit, 200MS/s, low DNL and INL, current-steering digital-to-analog converter (DAC) is proposed and analyzed. A novel feedback gain stage current mirror is proposed for improving the DAC’s differential non-linearity (DNL) and integral non-linearity (INL) characteristic. In the DAC design, good matching is an important element to maintain the resolution. The partition DAC architecture is used to reduce area and maintain the resolution. The proposed current-steering DAC is implemented based on the 0.25um 1 poly 5 metal CMOS process with 2.5V supply voltage. The MSB has 6 bits are made from segmented DAC structure, the LSB has 8 bits were made from R-2R ladder. After considering Vt, β mismatch and the post-layout simulation of Monte Carlo analysis, the DNL is between +0.28 and -0.26 LSB. The INL is between +0.1 and -0.1 LSB and the time of code transition is less than 5 ns, total power consumption is 54.4mW. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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