The Design of a High Speed Pipelined Analog-to-Digital Converter
| Autor: | Chang-Ting Wu, 吳昌庭 |
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| Rok vydání: | 2004 |
| Druh dokumentu: | 學位論文 ; thesis |
| Popis: | 92 In this thesis, a 8-bit, 80MHz sampling rate CMOS seven-stage pipelined analog-to-digital converter is designed with TSMC 0.35um 2p4m COMS process. The ADC consists of six 1.5-bit stages and the final stage is a 2-bit stage. Digital correction is used to relax the requirements on the Sub-ADCs. Fully differential structure is used to reduce the common-mode noise, and dummy device of switch is used to reduce the charge inject effect in the analog circuit design. Cancel offset structure is used to reduce the offset error effect in the MDAC design. Besides about digital circuit design, Manchester adder is used to reduce propagation delay time and gate count. According to the MATLAB simulation results, the static performance of differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.4LSB ~ -0.6LSB and 1.7LSB ~ -0.7LSB, respectively. The HSPICE simulation results show that the conversion time is about 56 ns and latency is 4.5 clock cycles. The two input range are from 0.9V to 1.7V that is the differential input range is from 0.8V to -0.8V. The Power supply of this ADC is 3.3V, and the simulation result show that ADC power dissipation is 52mW. |
| Databáze: | Networked Digital Library of Theses & Dissertations |
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