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Scaling the technology has resulted in smaller transistor sizes which increases the packing density of chips. The IC industry is moving from the conventional planar transistors (bulk CMOS) towards 3D transistor models such as FinFETs - due to its ease of fabrication, reduced leakage, process variations and short channel effects. In 2011, Intel came up with their first 3D transistor models in 22nm and in 2013, TSMC released their design flows for 16nm FinFET.The shift from the planar models to FinFETs were mainly due to the increase in leakage power with shrinking device dimensions. In FinFETs, the back gate of the transistor can be biased to control its Vth, thereby reducing the leakage power at the expense of performance. This research starts with the basic question of how to reduce the leakage power without degrading the performance. The key objective of this thesis is to propose such a design methodology for a special type of circuits called dynamic circuits, which are used in today’s high performance microprocessors due to its superior speed and reduced area.This thesis proposes MITH-Dyn, a novel multi Vth dynamic logic design style using mixed mode FinFETs which reduces the leakage power without degrading the performance. The proposed methodology has been tested on dynamic circuits of varying design complexity both in well known domino logic and np zipper logic. This thesis also extends the CMOS dynamic logic concepts such as C2MOS into FinFETs and proposes C2FinFET based latches and registers. MITH-Dyn has also been adapted to pipeline circuits which results in power optimized NORA (No Race) FinFET circuits. All the experiments throughout this thesis have been performed using the 45nm FinFET model cards provided by PTM. |
