| Popis: |
With device manufacturing entering the sub-micron technology while complexity of the circuits continues to grow, the different types of design errors and manufacturing errors also spread in variety. It remains important to have a fault model that properly emulates the large classes of problems which are most likely to occur throughout the design cycle. The implicit cube error replacement modeling is proposed to satisfy modeling of design errors, while maintaining a comparable or shorter fault list to current methods, such as explicit gate replacement and gate replacements with MIGSE modules. The proposed error modeling is also applied to functional testing of FPGAs, where the look-up table (LUT) based logic may contain an even larger variety of functional errors which the implicit cube error replacement modeling is used to check. Simulation techniques with random or upper-lattice layer vectors will be looked at, as well as incorporating satisfiability (SAT)-based automatic test pattern generation (ATPG) algorithms from the s-a-v model into the new model. A prototype implementation of the design-verification-testing flow of FPGA is also examined. |
