Autor: |
Yanbo Chen, Qiong Nie, Chaowei Zhong, Jiayi Song, Yinfeng Huang, Chengkai Lin, Qiming Zeng, Jie Cao, Yan Xue |
Jazyk: |
angličtina |
Rok vydání: |
2023 |
Předmět: |
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Zdroj: |
AIP Advances, Vol 13, Iss 2, Pp 025351-025351-6 (2023) |
Druh dokumentu: |
article |
ISSN: |
2158-3226 |
DOI: |
10.1063/5.0138835 |
Popis: |
This paper proposed an ultra-low-power successive approximation register analog to digital converter (ADC) for medical implant devices. To reduce power consumption, the novel techniques presented in this paper are a tri-state capacitor unit, a novel switch scheme, and a new low static power comparator. Tri-state capacitor unit reduces down power without the use of middle voltage reference. The proposed switch scheme can complete the most-significant bit 3-bit conversion without any power consumption. The offset of the low static power comparator is only optimized by physical design. This ADC is fabricated in a 110 nm 1P5M CMOS process. The reference voltage of DAC is 1 V, and the supply voltage of comparator and digital logic is 1.5 V. At 10 kS/s sampling rate, the signal to noise and distortion ratio (SNDR) is 57.57 dB and power consumption is 24 nW. |
Databáze: |
Directory of Open Access Journals |
Externí odkaz: |
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