| Autor: |
Aleksandr Cariow, Mariusz Naumowicz, Andrzej Handkiewicz |
| Jazyk: |
angličtina |
| Rok vydání: |
2024 |
| Předmět: |
|
| Zdroj: |
Applied Sciences, Vol 14, Iss 18, p 8123 (2024) |
| Druh dokumentu: |
article |
| ISSN: |
2076-3417 |
| DOI: |
10.3390/app14188123 |
| Popis: |
The paper presents the original structure of a processing unit for multiplying quaternions. The idea of organizing the device is based on the use of fast Hadamard transform blocks. The operation principles of such a device are described. Compared to direct quaternion multiplication, the developed algorithm significantly reduces the number of multiplication and addition operations. Hardware implementations of the developed structure, in FPGA and ASIC, are presented. The FPGA blocks were implemented in the Vivado environment. The ASICs were designed using 130nm technology. The developed scripts in VHDL are available in the GitHub repository. |
| Databáze: |
Directory of Open Access Journals |
| Externí odkaz: |
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